• FCCSP
FMCW mmWave Radar
• 57-66 GHz Coverage With 8 GHz Continuous Sweep Bandwidth
• 2 Transmit Channels and 4 Receive Channels
• Integrated RFPLL, DPLL, Transmitter, Receiver, ADC and Baseband
• 12.0 dBm Typical Output Power per TX
• 10.5dB Typical NF per RX
• -95 dBc/Hz typical Phase Noise at 1MHz
• 10/20MHz IF Bandwidth
• Up to 800MHz/us Ramp Rate
• HWA for 1D/2D FFT, Static Clutter Remove and CFAR Operations
2.4GHz Wireless Connectivity
• Protocols: Supports Bluetooth LE 5.3, Bluetooth Mesh, IEEE 802.15.4, Thread 1.3, Matter 1.1, and 2.4GHz proprietary
• Bluetooth LE PHY : 1Mbps, 2Mbps, Long Range S2 (500Kbps), S8 (125Kbps)
• TX Max Output Power: 10dBm@BLE mode
• RX Sensitivity: -95dBm @BLE 1Mbps
Application System
• Two 32-bit RISC-V CPU Cores with DSP, FPU (up to 256MHz) and I/D cache for Radar Post-processing, Wireless and Application
• Security Engine: Secure Boot, Efuse Key Protection, SRAM and XIP Decryption on the fly, TRNG, AES128/SHA/RSA/ECC
Memory
• On Chip 551KB SRAM
• External PSRAM Support (up to 16MB)
Power Management
• Single Power Supply from 1.7V to 5.5V
• Built-in LDO Network for Enhanced PSRR
• BOM-Optimized and Power-Optimized Modes
The RS6241 is a single chip 60GHz 2T4R FMCW MIMO radar sensor with 2.4GHz wireless connectivity(BLE5.3/802.15.4/Thread/Matter) inside. The device is portioned into four subsystems, shown in Figure below:
• mmWave Radar Subsystem: This block includes all high-performance radar RF/analog and baseband. It alsoincludes the chirp generator and tx-to-rx finite state machine. HWA is included in baseband, used tooffloadingspecified radar processing such as 1D/2D FFT and CFAR.
• 2.4GHz Wireless Connectivity Subsystem: This block contains whole 2.4G multi-protocol wireless RF, Mod/Demod, Baseband Protocol, and the data interacts with application CPU by internal data bus.
• Application Subsystem: It mainly includes two 32bit RISC-V CPU cores with DSP, FPU and I/D cache. CPUconnectsSRAM, peripheral interface, and other subsystems by AHB and APB bus. RISC-V CPU is used torunradarpost-processing algorithm, wireless protocol and other system tasks.
• Power and Clock Subsystem: This chip is complex single chip SoC with multiple function systems, we usesinglepower and clock subsystem to do centralized management. It includes several clock sources (including LSI, MSI, DCXO and SPLL), power blocks(LDOs, BG and Clamp) and temperature sensor.
RS6241 is specifically designed for high performance and low power radar sense system applications in industry. Itcontains four main power modes for low power management: shutdown, standby, idle and active. Its configurationanddata acquisition are enabled with UART/SPI/I2C/CAN-FD/LIN digital interface with other devices .
Enhanced Energy Efficiency:
• Dual-core RISC-V CPU with FPU/DSP extensions and built-in radar RSP hardware accelerator
• Power consumption <0.2W, no overheating
Superior Detection:
• 2T4R antenna array enables 4D sensing with advanced zone perception and zone division
• 2cm ultra-high range resolution for fine-grained micro-motion sensing (e.g., gestures, breathing/heart rate)
• 40m ultra-long detection range for large-space coverage
Simplified Development:
• 5-in-1 ultra-high integration (mmWave radar + multi-protocol wireless + PMU + SoC + AiP) with complete SDK and algorithm toolchain for one-stop development, reducing product development cycles and costs.
• Motion/Micro-Motion/Presence Detection
• Vital signs/Health monitoring
• Presence Detection
• Human Tracking/Counting
• Posture Recognition
• Industrial Detection
• Drone/Robot Obstacle Avoidance
• Cabin Inspection
• 6.7 x 6.7 x 0.87mm³
| Name | Related | Version |
Date
|
|---|---|---|---|
|
+
RS6241_Product_Brief_EN.pdf
This document provides users with a brief technical specification of the RS6241 SoC.
|
|
V1.0
V1.0
|
2024/12/28
|
| Name | Related | Version |
Date
|
|---|---|---|---|
|
+
RS6241_Product_Brief_EN.pdf
This document provides users with a brief technical specification of the RS6241 SoC.
|
|
V1.0
V1.0
|
2024/12/28
|











