FMCW mmWave Radar
• 76-81 GHz Sweep Frequency Coverage
• 2 Transmit Channels and 4 Receive Channels
• Integrated RFPLL, DPLL, Transmitter, Receiver, ADC and Baseband
• 11.5 dBm Typical Output Power per TX
• 11.5 dB Typical NF per RX
• -93 dBc/Hz typical Phase Noise at 1MHz
• 10MHz IF Bandwidth
• Up to 400MHz/us Ramp Rate
• HWA for 1D/2D FFT, Static Clutter Remove and CFAR Operations
Application System
• Two 32-bit RISC-V CPU Cores with DSP, FPU (up to 256MHz) and I/D cache for Radar Post-processing, Wireless and Application
• Security Engine: Secure Boot, Efuse Key Protection, SRAM and XIP Decryption on the fly, TRNG, AES128/SHA/RSA/ECC
Memory
• On Chip ROM and SRAM
• External PSRAM Support (up to 16MB)
Power Management
• Single Power Supply from 1.7V to 5.5V
• Built-in LDO Network for Enhanced PSRR
• BOM-Optimized and Power-Optimized Modes
The RS7241 is a single chip 77GHz 2T4R FMCW MIMO radar sensor. The device is portioned into three subsystems, shown in Figure below:
• mmWave Radar Subsystem: This block includes all high-performance radar RF/analog and baseband. It alsoincludes the chirp generator and tx-to-rx finite state machine. HWA is included in baseband, used tooffloadingspecified radar processing such as 1D/2D FFT and CFAR.
• Application Subsystem: It mainly includes two 32bit RISC-V CPU cores with DSP, FPU and I/D cache. CPUconnectsSRAM, peripheral interface, and other subsystems by AHB and APB bus. RISC-V CPU is used torunradarpost-processing algorithm and system tasks.
• Power and Clock Subsystem: This chip is complex single chip SoC with multiple function systems, we usesinglepower and clock subsystem to do centralized management. It includes several clock sources (including LSI, MSI, DCXO and SPLL), power blocks(LDOs, BG and Clamp) and temperature sensor.
RS7241 is designed for cost-effective radar sensing system applications in smart cars, two-wheelers, andindustrial sensing. It contains four main power modes for low power management: shutdown, standby, idle and active. Thehigh-performance dual-core CPU and external storage interface provide more powerful functions for high-performancecomplex algorithm application. Its configuration and data acquisition are enabled with UART/SPI/I2C/CAN-FDdigital Interface with other devices.
• Low Power: <0.2W full load, <1mW sentry mode
• Small Size: Modular size <30x30mm² with minimal peripherals
• Easy Development: Single-chip SoC + complete SDK for rapid deployment
• Blind Spot Detection (BSD)
• Auto Opening of Car Doors
• Kick-to-Open Tailgate
• Automated Parking
• Electric bicycles/motorcycles
• Industrial Detection
• Liquid Level Detection
• Robot Obstacle Avoidance
• 6.7 x 6.7 x 0.87mm³
• FCCSP
| Name | Related | Version |
Date
|
|---|---|---|---|
|
+
RS7241 Product Brief EN.pdf
This document provides users with a brief technical specification of the RS7241 chip.
|
|
V1.0
V1.0
|
2024/12/28
|
| Name | Related | Version |
Date
|
|---|---|---|---|
|
+
RS7241 Product Brief EN.pdf
This document provides users with a brief technical specification of the RS7241 chip.
|
|
V1.0
V1.0
|
2024/12/28
|











